VLSI Design Interview Questions & Answers

  1. Question 1. What Are Four Generations Of Integration Circuits?

    Answer :

    • SSI (Small Scale Integration)
    • MSI (Medium Scale Integration) 
    • LSI (Large Scale Integration)  
    • VLSI (Very Large Scale Integration)
  2. Question 2. Give The Advantages Of Ic?

    Answer :

    • Size is less 
    • High Speed  
    • Less Power Dissipation
  3. Perl Scripting Interview Questions

  4. Question 3. Give The Variety Of Integrated Circuits?

    Answer :

    • More Specialized Circuits  
    • Application Specific Integrated Circuits (ASICs) 
    • Systems-On-Chips
  5. Question 4. Give The Basic Process For Ic Fabrication?

    Answer :

    • Silicon wafer Preparation 
    • Epitaxial Growth 
    • Oxidation  
    • Photolithography 
    • Diffusion  
    • Ion Implantation  
    • Isolation technique 
    • Metallization  
    • Assembly processing & Packaging
  6. Perl Scripting Tutorial

  7. Question 5. What Are The Various Silicon Wafer Preparation?

    Answer :

    • Crystal growth & doping 
    • Ingot trimming & grinding  
    • Ingot slicing 
    • Wafer polishing & etching 
    • Wafer cleaning.
  8. Digital Electronics Interview Questions

  9. Question 6. Different Types Of Oxidation?

    Answer :

    Dry & Wet Oxidation

  10. Question 7. What Is The Transistors Cmos Technology Provides?

    Answer :

    N-type transistors & p-type transistors.

  11. Digital Communication Tutorial
    Verilog Interview Questions

  12. Question 8. What Are The Different Layers In Mos Transistors?

    Answer :

    Drain, Source & Gate

  13. Question 9. What Is Enhancement Mode Transistor?

    Answer :

    The device that is normally cut-off with zero gate bias.

  14. System Verilog Interview Questions

  15. Question 10. What Is Depletion Mode Device?

    Answer :

    The Device that conduct with zero gate bias.

  16. Question 11. When The Channel Is Said To Be Pinched – Off?

    Answer :

    If a large Vds is applied this voltage with deplete the Inversion layer. This Voltage effectively pinches off the channel near the drain.

  17. VHDL Interview Questions

  18. Question 12. Give The Different Types Of Cmos Process?

    Answer :

    • p-well process  
    • n-well process  
    • Silicon-On-Insulator Process  
    • Twin- tub Process
  19. Perl Scripting Interview Questions

  20. Question 13. What Are The Steps Involved In Twin-tub Process?

    Answer :

    • Tub Formation  
    • Thin-oxide Construction  
    • Source & Drain Implantation 
    • Contact cut definition 
    • Metallization.
  21. Question 14. What Are The Advantages Of Silicon-on-insulator Process?

    Answer :

    • No Latch-up.
    • Due to absence of bulks transistor structures are denser than bulk silicon.
  22. Question 15. What Is Bicmos Technology?

    Answer :

    It is the combination of bipolar technology & CMOS technology.

  23. Physical Design Engineer Interview Questions

  24. Question 16. What Are The Basic Processing Steps Involved In Bicmos Process?

    Answer :

    Additional masks defining P base region:

    • N Collector area  
    • Buried Sub collector (SCCD) 
    • Processing steps in CMOS process
  25. Question 17. What Are The Advantages Of Cmos Process?

    Answer :

    • Low power Dissipation 
    • High Packing density 
    • Bi directional capability
  26. Cmos Interview Questions

  27. Question 18. What Is The Fundamental Goal In Device Modeling?

    Answer :

    To obtain the functional relationship among the terminal electrical variables of the device that is to be modeled.

  28. Digital Electronics Interview Questions

  29. Question 19. Define Short Channel Devices?

    Answer :

    Transistors with Channel length less than 3- 5 microns are termed as Short channel devices. With short channel devices the ratio between the lateral & vertical dimensions are reduced.

  30. Question 20. What Is Pulling Down Device?

    Answer :

    A device connected so as to pull the output voltage to the lower supply voltage usually 0V is called pull down device.

  31. Digital Communication Interview Questions

  32. Question 21. What Is Pulling Up Device?

    Answer :

    A device connected so as to pull the output voltage to the upper supply voltage usually VDD is called pull up device.

  33. Question 22. Why Nmos Technology Is Preferred More Than Pmos Technology?

    Answer :

    N- Channel transistors has greater switching speed when compared tp PMOS transistors.

  34. Question 23. What Are The Different Operating Regions Foes An Mos Transistor?

    Answer :

    • Cutoff region 
    • Non- Saturated Region  
    • Saturated Region
  35. FPGA Interview Questions

  36. Question 24. What Are The Different Mos Layers?

    Answer :

    • N-diffusion  
    • P-diffusion  
    • Polysilicon  
    • Metal
  37. Verilog Interview Questions

  38. Question 25. What Is Stick Diagram?

    Answer :

    It is used to convey information through the use of color code. Also it is the cartoon of a chip layout.

  39. Question 26. What Are The Uses Of Stick Diagram?

    Answer :

    • It can be drawn much easier and faster than a complex layout.  
    • These are especially important tools for layout built from large cells.
  40. Question 27. Give The Various Color Coding Used In Stick Diagram?

    Answer :

    • Green – n-diffusion  
    • Red- Polysilicon  
    • Blue –metal  
    • Yellow- implant  
    • Black-contact areas.
  41. System Verilog Interview Questions

  42. Question 28. Compare Between Cmos And Bipolar Technologies?

    Answer :

    CMOS Technology:

    Low static power dissipation. High input impedance (low drive current). Scalable threshold voltage. High noise margin. High packing density. High delay sensitivity to load (fanout limitations). Low output drive current. Low gm (gm a VIN). Bidirectional capability. A near ideal switching device

    Bipolar technology:

    High power dissipation. Low input impedance (high drive current). Low voltage swing logic. Low packing density. Low delay sensitivity to load. High output drive current. High gm (gm an eVin). High ft at low current. Essentially unidirectional.

  43. Question 29. Define Threshold Voltage In Cmos?

    Answer :

    The Threshold voltage, VT for a MOS transistor can be defined as the voltage applied between the gate and the source of the MOS transistor below which the drain to source current, IDS effectively drops to zero.

  44. Question 30. What Is Body Effect?

    Answer :

    The threshold voltage VT is not a constant w. r. to the voltage difference between the substrate and the source of MOS transistor. This effect is called substrate-bias effect or body effect.

  45. Question 31. What Is Channel-length Modulation?

    Answer :

    The current between drain and source terminals is constant and independent of the applied voltage over the terminals. This is not entirely correct. The effective length of the conductive channel is actually modulated by the applied VDS, increasing VDS causes the depletion region at the drain junction to grow, reducing the length of the effective channel.

  46. Question 32. What Is Latch – Up?

    Answer :

    Latch up is a condition in which the parasitic components give rise to the establishment of low resistance conducting paths between VDD and VSS with disastrous results. Careful control during fabrication is necessary to avoid this problem.

  47. Question 33. Define Rise Time?

    Answer :

    Rise time, tr is the time taken for a waveform to rise from 10% to 90% of its steady-state value.

  48. VHDL Interview Questions

  49. Question 34. Define Fall Time?

    Answer :

    Fall time, tf is the time taken for a waveform to fall from 90% to 10% of its steady-state value.

  50. Question 35. Define Delay Time?

    Answer :

    Delay time, td is the time difference between input transition (50%) and the 50% output level. This is the time taken for a logic transition to pass from input to output.

  51. Question 36. What Are Two Components Of Power Dissipation?

    Answer :

    There are two components that establish the amount of power dissipated in a CMOS circuit.

    These are:

    1. Static dissipation due to leakage current or other current drawn continuously from the power supply.
    2. Dynamic dissipation due to.
    • Switching transient current.
    • Charging and discharging of load capacitances.
  52. Physical Design Engineer Interview Questions

  53. Question 37. Give Some Of The Important Cad Tools?

    Answer :

    Some of the important CAD tools are: 

    1. Layout editors 
    2. Design Rule checkers (DRC)
    3. Circuit extraction
  54. Question 38. What Is Verilog?

    Answer :

    Verilog is a general purpose hardware descriptor language. It is similar in syntax to the C programming language. It can be used to model a digital system at many levels of abstraction ranging from the algorithmic level to the switch level.

  55. Question 39. What Are The Various Modeling Used In Verilog?

    Answer :

    1. Gate-level modeling 
    2. Data-flow modeling 
    3. Switch-level modeling 
    4. Behavioral modeling
  56. Question 40. What Is The Structural Gate-level Modeling?

    Answer :

    Structural modeling describes a digital logic networks in terms of the components that make up the system. Gate-level modeling is based on using primitive logic gates and specifying how they are wired together.

  57. Cmos Interview Questions

  58. Question 41. What Is Switch-level Modeling?

    Answer :

    Verilog allows switch-level modeling that is based on the behavior of MOSFETs. Digital circuits at the MOS-transistor level are described using the MOSFET switches.

  59. Question 42. What Are Identifiers?

    Answer :

    Identifiers are names of modules, variables and other objects that we can reference in the design. Identifiers consists of upper and lower case letters, digits 0 through 9, the underscore character(_) and the dollar sign($). It must be a single group of characters. Examples: A014, a, b, in_o, s_out.

  60. Digital Communication Interview Questions

  61. Question 43. What Are The Value Sets In Verilog?

    Answer :

    Verilog supports four levels for the values needed to describe hardware referred to as value sets.

    Value levels Condition in hardware circuits:

    • 0 Logic zero, false condition 
    • 1 Logic one, true condition 
    • X Unknown logic value 
    • Z High impedance, floating state
  62. Question 44. What Are The Types Of Gate Arrays In Asic?

    Answer :

    1. Channeled gate arrays 
    2. Channel less gate arrays 
    3. Structured gate arrays
  63. Question 45. Give The Classifications Of Timing Control?

    Answer :

    Methods of timing control: 

    1. Delay-based timing control 
    2. Event-based timing control 
    3. Level-sensitive timing control

    Types of delay-based timing control: 

    1. Regular delay control 
    2. Intra-assignment delay control 
    3. Zero delay control 

    Types of event-based timing control: 

    1. Regular event control 
    2. Named event control 
    3. Event OR control 
    4. Level-sensitive timing control
  64. Question 46. What Are Gate Primitives?

    Answer :

    Verilog supports basic logic gates as predefined primitives. Primitive logic function keyword provides the basics for structural modeling at gate level. These primitives are instantiated like modules except that they are predefined in verilog and do not need a module definition. The important operations are and, nand, or, xor, xnor, and buf (non-inverting drive buffer).

  65. Question 47. Give The Two Blocks In Behavioral Modeling?

    Answer :

    1. An initial block executes once in the simulation and is used to set up initial conditions and step-by-step data flow.
    2. An always block executes in a loop and repeats during the simulation.
  66. Question 48. What Are The Types Of Conditional Statements?

    Answer :

    No else statement:

    Syntax: if ([expression]) true – statement; 

    One else statement: 

    Syntax: if ([expression]) true – statement; else false-statement; 

    Nested if-else-if:

    Syntax:

    • if ([expression1]) true statement 1; 
    • else if ([expression2]) true-statement 2;
    • else if ([expression3]) true-statement 3; 
    • else default-statement; 

    The [expression] is evaluated. If it is true (1 or a non-zero value) true-statement is executed. If it is false (zero) or ambiguous (x), the false-statement is executed.

  67. Question 49. Name The Types Of Ports In Verilog?

    Answer :

    • Input port Input 
    • Output port Output 
    • Bidirectional port inout
  68. Question 50. What Are The Types Of Procedural Assignments?

    Answer :

    1. Blocking assignment 
    2. Non-blocking assignment
  69. Question 51. Give The Different Types Of Asic?

    Answer :

    1. Full custom ASICs 

    2. Semi-custom ASICs:

    • Standard cell based ASICs. 
    • Gate-array based ASICs.

    3. Programmable ASICs: 

    • Programmable Logic Device (PLD).
    • Field Programmable Gate Array (FPGA).
  70. Question 52. What Is The Full Custom Asic Design?

    Answer :

    In a full custom ASIC, an engineer designs some or all of the logic cells, circuits or layout specifically for one ASIC. It makes sense to take this approach only if there are no suitable existing cell libraries available that can be used for the entire design.

  71. Question 53. What Is The Standard Cell-based Asic Design?

    Answer :

    A cell-based ASIC (CBIC) uses predesigned logic cells known as standard cells. The standard cell areas also called fle4xible blocks in a CBIC are built of rows of standard cells. The ASIC designer defines only the placement of standard cells and the interconnect in a CBIC. All the mask layers of a CBIC are customized and are unique to a particular customer.

  72. Question 54. Differentiate Between Channeled & Channel Less Gate Array?

    Answer :

    Channeled Gate Array: Only the interconnect is customized. The interconnect uses predefined spaces between rows of base cells. Routing is done using the spaces. Logic density is less

    Channel less Gate Array: Only the top few mask layers are customized. No predefined areas are set aside for routing between cells. Routing is done using the area of transistors unused. Logic density is higher.

  73. Question 55. Give The Constituent Of I/o Cell In 22v10?

    Answer :

    2V10 I/O cell consists of:

    1. A register 
    2. An output 4:1 mux 
    3. A tristate buffer 
    4. A 2:1 input mux 

    It has the following characteristics: 

    • 12 inputs 
    • 10 I/Os 
    • Product time 9 10 12 14 16 14 12 10 8 
    • 24 pins
  74. Question 56. What Is A Fpga?

    Answer :

    A field programmable gate array (FPGA) is a programmable logic device that supports implementation of relatively large logic circuits. FPGAs can be used to implement a logic circuit with more than 20,000 gates whereas a CPLD can implement circuits of upto about 20,000 equivalent gates.

  75. Question 57. What Are The Different Methods Of Programming Of Pals?

    Answer :

    The programming of PALs is done in three main ways:

    • Fusible links
    • UV – erasable EPROM
    • EEPROM (EePROM) – Electrically Erasable Programmable ROM
  76. Question 58. What Is An Antifuse?

    Answer :

    An antifuse is normally high resistance (>100MW). On application of appropriate programming voltages, the antifuse is changed permanently to a low-resistance structure (200-500W).

  77. Question 59. What Are The Different Levels Of Design Abstraction At Physical Design?

    Answer :

    • Architectural or functional level
    • Register Transfer-level (RTL)
    • Logic level
    • Circuit level
  78. Question 60. What Are Macros?

    Answer :

    The logic cells in a gate-array library are often called macros.

  79. Question 61. What Is Programmable Interconnects?

    Answer :

    In a PAL, the device is programmed by changing the characteristics if the switching element. An alternative would be to program the routing.

  80. Question 62. Give The Steps In Asic Design Flow?

    Answer :

    • Design entry 
    • Logic synthesis System partitioning 
    • Pre layout simulation. 
    • Floor planning 
    • Placement 
    • Routing
    • Extraction 
    • Post layout simulation
  81. Question 63. Mention The Levels At Which Testing Of A Chip Can Be Done?

    Answer :

    • At the wafer level 
    • At the packaged-chip level 
    • At the board level 
    • At the system level 
    • In the field
  82. Question 64. What Are The Categories Of Testing?

    Answer :

    • Functionality tests 
    • Manufacturing tests
  83. Question 65. Write Notes On Functionality Tests?

    Answer :

    Functionality tests verify that the chip performs its intended function. These tests assert that all the gates in the chip, acting in concert, achieve a desired function. These tests are usually used early in the design cycle to verify the functionality of the circuit.

  84. Question 66. Write Notes On Manufacturing Tests?

    Answer :

    Manufacturing tests verify that every gate and register in the chip functions correctly. These tests are used after the chip is manufactured to verify that the silicon is intact.

  85. Question 67. Mention The Defects That Occur In A Chip?

    Answer :

    • Layer-to-layer shorts 
    • Discontinuous wires 
    • Thin-oxide shorts to substrate or well
  86. Question 68. Give Some Circuit Maladies To Overcome The Defects?

    Answer :

    • Nodes shorted to power or ground 
    • Nodes shorted to each other 
    • Inputs floating/outputs disconnected
  87. Question 69. What Are The Tests For I/o Integrity?

    Answer :

    • I/O level test 
    • Speed test 
    • IDD test
  88. Question 70. What Is Meant By Fault Models?

    Answer :

    Fault model is a model for how faults occur and their impact on circuits.

  89. Question 71. Give Some Examples Of Fault Models?

    Answer :

    • Stuck-At Faults.
    • Short-Circuit and Open-Circuit Faults.
  90. Question 72. What Is Stuck – At Fault?

    Answer :

    With this model, a faulty gate input is modeled as a “stuck at zero” or “stuck at one”. These faults most frequently occur due to thin -oxide shorts or metal-to-metal shorts.

  91. Question 73. What Is Meant By Observability?

    Answer :

    The observability of a particular internal circuit node is the degree to which one can observe that node at the outputs of an integrated circuit.

  92. Question 74. What Is Meant By Controllability?

    Answer :

    The controllability of an internal circuit node within a chip is a measure of the ease of setting the node to 1 or 0 states.

  93. Question 75. What Is Known As Percentage-fault Coverage?

    Answer :

    The total number of nodes that, when set to 1 or 0, do result in the detection of the fault, divided by the total number of nodes in the circuit, is called the percentage-fault coverage.

  94. Question 76. What Is Fault Grading?

    Answer :

    Fault grading consists of two steps. First, the node to be faulted is selected. A simulation is run with no faults inserted, and the results of this simulation are saved. Each node or line to be faulted is set to 0 and then 1 and the test vector set is applied. If and when a discrepancy is detected between the faulted circuit response and the good circuit response, the fault is said to be detected and the simulation is stopped.

  95. Question 77. Mention The Ideas To Increase The Speed Of Fault Simulation?

    Answer :

    • Parallel simulation 
    • Concurrent simulation
  96. Question 78. What Is Fault Sampling?

    Answer :

    An approach to fault analysis is known as fault sampling. This is used in circuits where it is impossible to fault every node in the circuit. Nodes are randomly selected and faulted. The resulting fault detection rate may be statistically inferred from the number of faults that are detected in the fault set and the size of the set. The randomly selected faults are unbiased. It will determine whether the fault coverage exceeds a desired level.

  97. Question 79. What Are The Approaches In Design For Test Ability?

    Answer :

    • Ad hoc testing 
    • Scan-based approaches
    • Self-test and built-in testing
  98. Question 80. Mention The Common Techniques Involved In Ad Hoc Testing?

    Answer :

    • Partitioning large sequential circuits 
    • Adding test points 
    • Adding multiplexers 
    • Providing for easy state reset
  99. Question 81. What Are The Scan-based Test Techniques?

    Answer :

    • Level sensitive scan design 
    • Serial scan 
    • Partial serial scan 
    • Parallel scan
  100. Question 82. What Are The Two Tenets In Lssd?

    Answer :

    The circuit is level-sensitive. Each register may be converted to a serial shift register.

  101. Question 83. What Are The Self-test Techniques?

    Answer :

    • Signature analysis and BILBO 
    • Memory self-test 
    • Iterative logic array testing
  102. Question 84. What Is Known As Bilbo?

    Answer :

    Signature analysis can be merged with the scan technique to create a structure known as BILBO- for Built in Logic Block Observation.

  103. Question 85. What Is Known As Iddq Testing?

    Answer :

    A popular method of testing for bridging faults is called IDDQ or current supply monitoring. This relies on the fact that when a complementary CMOS logic gate is not switching, it draws no DC current. When a bridging fault occurs, for some combination of input conditions a measurable DC IDD will flow.

  104. Question 86. What Are The Applications Of Chip Level Test Techniques?

    Answer :

    • Regular logic arrays 
    • Memories 
    • Random logic
  105. Question 87. What Is Boundary Scan?

    Answer :

    The increasing complexity of boards and the movement to technologies like multichip modules and surface-mount technologies resulted in system designers agreeing on a unified scan-based methodology for testing chips at the board. This is called boundary scan.

  106. Question 88. What Is The Test Access Port?

    Answer :

    The Test Access Port (TAP) is a definition of the interface that needs to be included in an IC to make it capable of being included in boundary-scan architecture.

    The port has four or five single bit connections, as follows:

    • TCK (The Test Clock Input)
    • TMS (The Test Mode Select)
    • TDI (The Test Data Input)
    • TDO (The Test Data Output)

     It also has an optional signal:

    • TRST*(The Test Reset Signal)
  107. Question 89. What Are The Contents Of The Test Architecture?

    Answer :

    The test architecture consists of:

    • The TAP interface pins
    • A set of test-data registers
    • An instruction register
    • A TAP controller
  108. Question 90. What Is The Tap Controller?

    Answer :

    The TAP controller is a 16-state FSM that proceeds from state to state based on the TCK and TMS signals. It provides signals that control the test data registers, and the instruction register. These include serial-shift clocks and update clocks.

  109. Question 91. What Is Known As Test Data Register?

    Answer :

    The test-data registers are used to set the inputs of modules to be tested, and to collect the results of running tests.

  110. Question 92. What Is Known As Boundary Scan Register?

    Answer :

    The boundary scan register is a special case of a data register. It allows circuit-board interconnections to be tested, external components tested, and the state of chip digital I/Os to be sampled.