VHDL Interview Questions & Answers

  1. Question 1. What Is Vhdl?

    Answer :

    VHDL stands for “VHSIC Hardware Description Language.” VHSIC, in turn, stands for “Very High Speed Integrated Circuit,” which was a U.S. Department of Defense program.

  2. Question 2. What Can Be The Various Uses Of Vhdl?

    Answer :

    The VHDL language can be used for several goals like –

    1. To synthesize digital circuits.
    2. To verify and validate digital designs.
    3. To generate test vectors to test circuits.
    4. To simulate circuits.
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  4. Question 3. Explain Various Types Of Delays In Vhdl ?

    Answer :

    The Various types of delays in VHDL are :-

    1. Delta delay – In VHDL simulations, all signal assignments occur with some infinitesimal delay, known as delta delay. VHDL uses the concept of delta delay to keep track of processes that should occur at a given time step,but are actually evaluated in different machine cycles .A delta delay is a unit of time as far as the simulator hardware is concerned, but in the simulation itself time has no advance. Technically, delta delay is of no measurable unit, but from a hardware design perspective one should think of delta delay as being the smallest time unit one could measure, such as a femtosecond(fs).

    2. Inertial delay – The inertial delay causes the pulses less than specified delay to get suppressed & will not propogate these pulses to change the output. The inertial delay model is specified by adding an after clause to the signal assignment statement. Inertial delay is basically a default delay, i.e it’s a component delay.

    3. Transport delay – Tranport delay adds the propogation delay to the signal. The transport delay model just delays the change in the output by the time specified in the after clause. Transport delay basically represents a wire delay. 
    e.g. q <=transport a nor b after 1ns ;

  5. Question 4. What Are Generics?

    Answer :

    Generics are a way to provide static information to the VHDL program. Immediately after writing entity name, we will mention the generics, this generics will provide the data for entire program. Generics basically allow a design entity to be described so that,for each use of that component,its structure and behavior can be changed by generic values.In general they are used to construct parameterized hardware components.Generics can be of any type.but mostly we will give the timing details there. 
    E.g. :- generic ( width : integer := 7 );

    Generic is a great asset when you use your design at many places with slight change in the register sizes,input sizes etc. But if the design is very unique then,you need not have generic parameters. Also, Generic’s are synthesizable.

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  7. Question 5. What Is The Difference Between Concurrent & Sequential Statements?

    Answer :

    Concurrent statements define interconnected processes and blocks that together describe a design’s overall behavior or structure. They can be grouped using block statement. Groups of blocks can also be partitioned into other blocks. At the same level, a VHDL component can be connected to define signals within the blocks It is a reference to an entity A process can be a single signal assignment statement or a series of sequential statements (SS) Within a process, procedures and functions can partition the sequential statements.

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  9. Question 6. Are Verilog/vhdl Concurrent Or Sequential Language In Nature?

    Answer :

    Verilog and VHDL both are concurrent languages. Any hardware descriptive language is concurrent in nature.

  10. Question 7. How Do You Implement Multiply And Divide Operation With Power Of 2 In Vhdl?

    Answer :

    Left shift is equivalent to multiply operation and right shift is equivalent to divide operation. Hence using shift operations the same can be easily and efficiently implemented. 

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  12. Question 8. What Is A D-latch?

    Answer :

    D latch is a device it simply transfers data from input to output when the enable is activated.its used for the forming of d flip flops.

  13. Question 9. What Is The Use Of Subtype In Vhdl?

    Answer :

    Subtype is mainly used for range checking and for imposing additional constraints ontypes.

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  15. Question 10. List Out All Ieee Standard Libraries Available In Vhdl?

    Answer :

    1. std_logic_1164.
    2. numeric_std.
    3. numeric_bit.
    4. std_logic_arith.
    5. std_logic_unsigned.
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  17. Question 11. Which Is The Default Delay In Vhdl?

    Answer :

    delta delay.

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  19. Question 12. What Is Propagation Delay?

    Answer :

    Transport delay models the behavior of a wire, in which all pulses are propagatedirrespective there width.

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  21. Question 13. What Is Inertial Delay?

    Answer :

    This is the delay often found in switching circuits where spikes will not propogatefurther in circuit.

  22. Question 14. How Will You Specify The Delay In Vhdl?

    Answer :

    using after clause.

  23. Question 15. Mention The Two Delays In Vhdl?

    Answer :

    1. Inertial delay 
    2. Transport delay.
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  25. Question 16. What Is An Alias And Write Its Syntax?

    Answer :

    Alias is an alternative name assigned to part of an object. alias alias_name : subtype isname

  26. Question 17. What Is The Difference Between Array And Record?

    Answer :

    Array contain many elements of the same type. But Record contains many elements of different types.

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  28. Question 18. Which Are The Two Composite Types?

    Answer :

    Array and Record.

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  30. Question 19. Which Are The Major Data Types In Vhdl?

    Answer :

    Scalar Types and Composite Types.

  31. Question 20. List Out The Objects Of Vhdl?

    Answer :

    Signal, Variable, Constant.

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  33. Question 21. Is That Object Of Type Real Is Supported In Vhdl? And Mention The Reason?

    Answer :

    No, because floating point numbers cannot be mapped to hardware.

  34. Question 22. What Are Signals?

    Answer :

    Signals are like a wires which connect design entities together and communicatechanges in values within a design.

  35. Question 23. List Out The Four Modes For Port In Vhdl?

    Answer :


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  37. Question 24. List Out The Levels Of Abstractions In Vhdl?

    Answer :

    Data flow level, Structural Level, Behavioral Level.

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  39. Question 25. Which Type Of Assignment Statements Will Be Used In Data Flow Level And Behavioural Level?

    Answer :

     Concurrent statements will be used in data flow level and Sequential statements will beused in behavioral level.

  40. Question 26. What Is The Difference Between Sequential Circuit And Combinational Circuit?

    Answer :

    Sequential circuit uses flip flops. Sequential circuits have state, which means basicallythey have memory. They compute the output based on input and the state and updated basedon clocks. A combinational circuit does not have any states. They are functions of only inputs but not clocks. They are basically used to implement Boolean function.

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  42. Question 27. What Do We Need To Generate Hardware From Vhdl Model?

    Answer :

    We need following tools

    1. Simulation tool.
    2. Synthesis tool.
    3. Implementation tool.
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  44. Question 28. What Are The Properties Of Signal?

    Answer :

    Type and Type attributes, value, time.

  45. Question 29. Which Is The Signal Assignment Operator?

    Answer :

    “ < = “.

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  47. Question 30. How The Signal Acts Within A Process And Outside The Process?

    Answer :

    Signal assignment is concurrent outside the process and sequential within a process.