Universal Verification Methodology (UVM) Interview Questions & Answers

  1. Question 1. What Is Uvm? What Is The Advantage Of Uvm?

    Answer :

    UVM (Universal Verification Methodology) is a standardized methodology for verifying the both complex & simple digital design in simple way.

    UVM Features:

    • First methodology & second collection of class libraries for Automation
    • Reusability through test bench
    • Plug & Play of verification IPs
    • Generic Test bench Development
    • Vendor & Simulator Independent
    • Smart Test bench i.e. generate legal stimulus as from pre-planned coverage plan
    • Support CDV –Coverage Driven Verification
    • Support CRV –Constraint Random Verification
    • UVM standardized under the Accelerate System Initiative
    • Register modeling
  2. Question 2. Uvm Derived From Which Language?

    Answer :

    Here is the detailed connection between SV, UVM, OVM and other methodologies.

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  4. Question 3. What Is The Difference Between Uvm_component And Uvm_object?
    Or
    We Already Have Uvm_object, Why Do We Need Uvm_component Which Is Actually Derived Class Of Uvm_object?

    Answer :

    uvm_component:

    • Quasi Static Entity (after build phase it is available throughout the simulation).
    • Always tied to a given hardware (DUT Interface) or a TLM port.
    • Having phasing mechanism for control the behavior of simulation.
    • Configuration Component Topology.

    uvm_object:

    • Dynamic Entity (creates when needed, transfer from one component to other & then dereference).
    • Not tied to a given hardware or any TLM port.
    • Not phasing mechanism.
  5. Question 4. Which Uvm Phase Is Top – Down, Bottom – Up & Parallel?

    Answer :

    Only build phase is a top-down & other phases are bottom-up except run phase which is parallel. The build phase works top-down since the test bench hierarchy may be configure so we need to build the branches before leafs.

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  7. Question 5. Why Build Phase Is Top – Down & Connect Phase Is Bottom – Up?

    Answer :

    The connect phase is intended to be used for making TLM connections between components, which is why it occur after build phase. It work bottom-up so that its got the correct implementation all the way up the design hierarchy, if worked top-down this would be not possible.

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  9. Question 6. Which Phase Is Function & Which Phase Is Task?

    Answer :

    Only run phase is a task (time consuming phase) & other phases are functions (non-blocking).

  10. Question 7. Which Phase Takes More Time And Why?

    Answer :

    As previously said the run phase is implemented as task and remaining all are function. run phase will get executed from start of simulation to till the end of simulation. run phase is time consuming, where the test case is running.

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  12. Question 8. How Uvm Phases Initiate?

    Answer :

    UVM phases initiate by calling run test (“test1”) in top module. When run test() method call, it first create the object of test top & then call all phases.

  13. Question 9. How Test Cases Run From Simulation Command Line?

    Answer :

    In top module write run test(); i.e. Don’t give anything in argument.

    Then in command line: +UVM_TESTNAME=test name.

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  15. Question 10. Difference Between Module & Class Based Tb?

    Answer :

    • A module is a static object present always during of the simulation.
    • A Class is a dynamic object because they can come and go during the life time of simulation.
  16. Question 11. What Is Uvm_config_db? What Is Difference Between Uvm_config_db & Uvm_resource_db?

    Answer :

    • Uvm_config_db is a parameterized class used for configuration of different type of parameter into the uvm database, So that it can be used by any component in the lower level of hierarchy.
    • Uvm_config_db is a convenience layer built on top of uvm_resource_db, but that convenience is very important. In particular, uvm_resource_db uses a “last write wins” approach. The uvm_config_db, on the other hand, looks at where things are in the hierarchy up through end_of_elaboration, so “parent wins.” Once you start start_of_simulation, the config_db becomes “last write wins.”
    • All of the functions in uvm_config_db#(T) are static, so they must be called using the :: operator. It is extended from the uvm_resource_db#(T), so it is child class of uvm_resource_db#(T).
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  18. Question 12. What Is The Advantage And Difference Of `uvm_component_utils() And `uvm_object_utils()?

    Answer :

    • The utile macros define the infrastructure needed to enable the object/component for correct factory operation. 
    • The reason there are two macros is because the factory design pattern fixes the number of arguments that a constructor can have. Classes derived from uvm_object have constructors with one argument, a string name. Classes derived from uvm_component have two arguments, a name and a uvm_component parent.  
    • The two `uvm_*utile macros inserts code that gives you a factory create() method that delegates calls to the constructors of uvm_object or uvm_component. You need to use the respective macro so that the correct constructor arguments get passed through. This means that you cannot add extra constructor arguments when you extend these classes in order to be able to use the UVM factory.
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  20. Question 13. Difference Between `uvm_do And `uvm_rand_send ?

    Answer :

    uvm_do perform the below steps:

    1. Create
    2. Start item
    3. Randomize
    4. Finish item
    5. get response (optional)

    While `uvm_rand_send perform all the above steps except create. User needs to create sequence / sequence item.

  21. Question 14. Difference Between Uvm_transaction And Uvm_seq_item?

    Answer :

    class uvm_sequence_item extends uvm_transaction

    Uvm_sequence_item extended from uvm_transaction only, uvm_sequence_item class has more functionality to support sequence & sequencer features. Uvm_sequence_item provides the hooks for sequencer and sequence, So you can generate transaction by using sequence and sequencer , and uvm_transaction provide only basic methods like do print and do record etc .

  22. Question 15. Is Uvm Is Independent Of Systemverilog?

    Answer :

    UVM is a methodology based on Systemverilog language and is not a language on its own.  It is a standardized methodology that defines several best practices in verification to enable efficiency in terms of reuse and is also currently part of IEEE 1800.2 working group.

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  24. Question 16. What Are The Benefits Of Using Uvm?

    Answer :

    Some of the benefits of using UVM are:

    • Modularity and Reusability – The methodology is designed as modular components (Driver, Sequencer, Agents , env etc) which enables reusing components across unit level to multi-unit or chip level verification as well as across projects.
    • Separating Tests from Test benches – Tests in terms of stimulus/sequencers are kept separate from the actual test bench hierarchy and hence there can be reuse of stimulus across different units or across projects.
    • Simulator independent – The base class library and the methodology is supported by all simulators and hence there is no dependence on any specific simulator.
    • Better control on Stimulus generation – Sequence methodology gives good control on stimulus generation. There are several ways in which sequences can be developed which includes randomization, layered sequences, virtual sequences etc which provides a good control and rich stimulus generation capability.
    • Easy configuration – Config mechanisms simplify configuration of objects with deep hierarchy. The configuration mechanism helps in easily configuring different test bench components based on which verification environment uses it and without worrying about how deep any component is in test bench hierarchy.
    • Factory mechanism – Factory mechanisms simplifies modification of components easily. Creating each components using factory enables them to be overridden in different tests or environments without changing underlying code base.
  25. Question 17. Can We Have User Defined Phase In Uvm?

    Answer :

    In addition to the predefined phases available in uvm , the user has the option to add his own phase to a component. This is typically done by extending the uvm_phase class the constructor needs to call super. new which has three arguments.

    • Name of the phase task or function
    • Top down or bottom up phase
    • Task or function

    The call task or call_func and get_type_name need to be implemented to complete the addition of new phase.

    Below is a simple example 

    Example:

    Class custom phase extends uvm_phase;

       Function new ();

          Super. New (“custom”, 1, 1);

       End function

      Task call task (uvm_component parent);

         My_comp_type comp;

         If ( $cast(comp, parent) )

                 comp.custom phase ();

       End task

       Virtual function string get_type_name ();

          Return “custom”;

       End function

    End class

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  27. Question 18. What Is Uvm Ral Model? Why It Is Required?

    Answer :

    In a verification context, a register model (or register abstraction layer) is a set of classes that model the memory mapped behavior of registers and memories in the DUST in order to facilitate stimulus generation and functional checking (and optionally some aspects of functional coverage). The UVM provides a set of base classes that can be extended to implement comprehensive register modeling capabilities.

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  29. Question 19. What Is The Difference Between New() And Create?

    Answer :

    We all know about new () method that is use to allocate memory to an object instance. In UVM (and OVM), the create () method causes an object instance to be created from the factory. This allows you to use factory overrides to replace the desired object with an object of a different type without having to recode.

  30. Question 20. What Is Analysis Port?

    Answer :

    Analysis port (class uvm_tlm_analysis_port) — a specific type of transaction-level port that can be connected to zero, one, or many analysis exports and through which a component may call the method write implemented in another component, specifically a subscriber.

    port, export, and imp classes used for transaction analysis.

    uvm_analysis_port

    Broadcasts a value to all subscribers implementing a uvm_analysis_imp.

    uvm_analysis_imp

    Receives all transactions broadcasted by a uvm_analysis_port.

    uvm_analysis_export

    Exports a lower-level uvm_analysis_imp to its parent.

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  32. Question 21. What Is Tlm Fifo?

    Answer :

    In simpler words TLM FIFO is a FIFO between two UVM components, preferably between Monitor and Scoreboard. Monitor keep on sending the DATA, which will be stored in TLM FIFO, and Scoreboard can get data from TLM FIFO whenever needed.

    // create a FIFO with depth 4

       tlm_fifo = new (“uvm tlm_fifo”, this, 4);

  33. Question 22. How Sequence Starts?

    Answer :

    Start item starts the sequence

    Virtual task start item (uvm_sequence_item item,   

    int set priority  =  -1,

    Uvm_sequencer_base sequencer =  null )

    Start item and finish item together will initiate operation of a sequence item.  If the item has not already been initialized using create item, then it will be initialized here to use the default sequencer specified by m_sequencer.

  34. Question 23. What Is The Difference Between Uvm Ral Model Backdoor Write/read And Front Door Write/read?

    Answer :

    • Font door access means using the standard access mechanism external to the DUTY to read or write to a register. This usually involves sequences of time-consuming transactions on a bus interface. 
    • Backdoor access means accessing a register directly via hierarchical reference or outside the language via the PLI. A backdoor reference usually in 0 simulation time.
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  36. Question 24. What Is Objection?

    Answer :

    • The objection mechanism in UVM is to allow hierarchical status communication among components which is helpful in deciding the end of test.
    • There is a built-in objection for each in-built phase, which provides a way for components and objects to synchronize their testing activity and indicate when it is safe to end the phase and, ultimately, the test end.
    • The component or sequence will raise a phase objection at the beginning of an activity that must be completed before the phase stops, so the objection will be dropped at the end of that activity. Once all of the raised objections are dropped, the phase terminates.

    Raising an objection: phase.raise_objection (this);

    Dropping an objection: phase.drop_objection (this);

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  38. Question 25. What Is M_sequencer? Or Difference Between M_sequencer And M_sequencer?

    Answer :

    M_sequencer is the default handle for uvm_vitual_sequencer and m_sequencer is the hook up for child sequencer.

    M_sequencer is the generic uvm_sequencer pointer. It will always exist for the uvm_sequencer and is initialized when the sequence is started.

    P_sequencer is a typed-specific sequencer pointer, created by registering the sequence to the sequencer using macros (`uvm_declare_p_sequencer) . Being type specific, you will be able to access anything added to the sequencer (i.e. pointers to other sequencers, etc.). M_sequencer will not exist if we have not registered the sequence with the `uvm_declare_p_sequencer macros.

    The drawback of m_sequencer is that once the m_sequencer is defined, one cannot run the sequence on any other sequencer type.

  39. Question 26. What Is The Difference Between Active Mode And Passive Mode With Respect To Agent?

    Answer :

    An agent is a collection of a sequencer, a driver and a monitor.

    In active mode, the sequencer and the driver are constructed and stimulus is generated by sequences sending sequence items to the driver through the sequencer. At the same time the monitor assembles pin level activity into analysis transactions.

    In passive mode, only the monitor is constructed and it performs the same function as in an active agent. Therefore, your passive agent has no need for a sequencer. You can set up the monitor using a configuration object.

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  41. Question 27. What Is The Difference Between Copy And Clone?

    Answer :

    The built-in copy () method executes the __m_uvm_field_automation() method with the required copy code as defined by the field macros (if used) and then calls the built-in do copy() virtual function. The built-in do copy () virtual function, as defined in the uvm_object base class, is also an empty method, so if field macros are used to define the fields of the transaction, the built-in copy() method will be populated with the proper code to copy the transaction fields from the field macro definitions and then it will execute the empty do copy() method, which will perform no additional activity.

    The copy() method can be used as needed in the UVM test bench. One common place where the copy() method is used is to copy the sampled transaction and pass it into a sb_calc_exp() (scoreboard calculate expected) external function that is frequently used by the scoreboard predictor.

    The clone () method calls the create () method (constructs an object of the same type) and then calls the copy() method. It is a one-step command to create and copy an existing object to a new object handle.

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  43. Question 28. What Is Uvm Factory?

    Answer :

    UCM Factory is used to manufacture (create) UVM objects and components. Apart from creating the UVM objects and components the factory concept essentially means that you can modify or substitute the nature of the components created by the factory without making changes to the test bench. 

    For example, if you have written two driver classes, and the environment uses only one of them. By registering both the drivers with the factory, you can ask the factory to substitute the existing driver in environment with the other type. The code needed to achieve this is minimal, and can be written in the test.

  44. Question 29. What Are The Types Of Sequencer? Explain Each?

    Answer :

    There are two types of sequencers:

    uvm_sequencer #(REQ, RSP) :

    When the driver initiates new requests for sequences, the sequencer selects a sequence from a list of available sequences to produce and deliver the next item to execute. In order to do this, this type of sequencer is usually connected to a driver uvm_driver #(REQ, RSP).

    uvm_push_sequencer #(REQ, RSP) :

    The sequencer pushes new sequence items to the driver, but the driver has the ability to block the item flow when it’s not ready to accept any new transactions. This type of sequencer is connected to a driver of type uvm_push_driver # (REQ, RSP).

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